1. Field of the Invention
The present invention relates to a digital-to-analog converter (DAC) and to an active matrix liquid crystal display (AMLCD) incorporating such a DAC.
2. Description of the Related Art
A known type of DAC comprises two cascaded stages in which the first stage selects a pair of low-impedance reference voltages from a plurality of voltage references and supplies these as inputs to a second stage linear DAC. DACs of this type are, for example, used in data driver control circuits of AMLCDs with digital interfaces Such converters are used to generate the analog picture element (pixel) voltages and to provide compensation for the non-linear relationship between pixel voltage and pixel light transmission of a liquid crystal pixel. This is generally referred to as gamma correction and is used effectively to linearise the relationship between pixel voltage and pixel transmission.
FIG. 1 of the accompanying drawings illustrates a known type of two stage DAC, for example as disclosed in U.S. Pat. No. 5,877,717. The first stage 1 has 2m+1 inputs which are connected to low-impedance reference voltage sources for providing a zero reference voltage and 2m different reference voltages representing the end points of linear segments of a linear segment approximation to a function for providing gamma correction. The first stage 1 functions as a DAC and receives the m most significant bits (MSBs) of a k bit parallel input signal. An m-to-2m decoder converts the m MSBs so as to supply an active signal on the corresponding one of the 2m outputs and these are used to control two 2m-to-1 multiplexers. The m MSBs thus select reference voltages VH and VL corresponding to one of the line segments.
The second stage 2 comprises a linear DAC which is addressed by the n least significant bits (LSBs) of the k bits of the input signal and performs an n-bit linear conversion in the voltage range defined by the upper and lower voltage limits VH and VL. The DAC 2 comprises an n-to-2n decoder 2a whose outputs control n switches such as 3 for selecting the tapping points of a resistive potential divider comprising resistors such as 4 connected in series between the DAC inputs receiving the voltages VH and VL The output of the DAC 2 is connected, either directly or via an optional buffer 5 shown in broken lines in FIG. 1, to a load, which is illustrated as a capacitive load CLOAD.
FIG. 2 of the accompanying drawings illustrates another known two stage converter of the type disclosed in EP 0 899 884. This DAC differs from the one shown in FIG. 1 in that the second stage 2 uses a capacitive converter instead of a resistive ladder converter. The n LSBs directly control n electronic switches such as 6 which selective connect the first electrodes of respective capacitors such as 7 to receive the upper voltage VH or the lower voltage VL from the first stage DAC 1. The second electrodes of the capacitors are connected together and, directly or via the optional buffer 5, to the output of the DAC. Further switches such as 8 are connected across the capacitors and a switch 9 is connected between the second electrodes of the capacitors 7 and the input receiving the lower voltage VL.
The capacitors 7 have binary scaled capacitances such that the capacitance of each capacitor is twice that of the capacitor representing the next least significant bit. The switches 6, 8 and 9 are controlled by a two-phase non-overlapping clock having phases indicated in FIG. 2 as "PHgr"1 and "PHgr"2. During the first phase "PHgr"1. the switches 8 and 9 are closed so as to discharge the capacitors 7 and charge the output of the converter 2 to the lower voltage VL. During the second clock phase "PHgr"2, each capacitor 7 is connected to receive the higher voltage VH if its control bit is high or to the lower voltage VL if its control bit is low.
Two of the important specifications of a DAC are the precision with which the input digital data are converted to the corresponding analog value and the speed of conversion (into a given load impedance). The use of the buffer 5 is advantageous in increasing the drive capability and thus the overall speed of conversion. However, for high speed converters driving high capacitance loads, for example in AMLCDs, this may place a high slew-rate and accuracy requirement on the buffer.
In order to increase the speed of the conversion process, it is known to perform a precharge of the output load to an intermediate level, for example as disclosed in U.S. Pat. No. 5,426,447. Such an arrangement is illustrated in FIG. 3 of the accompanying drawings, which shows an AMLCD including a thin film transistor (TFT) array 10. The array 10 comprises thin film transistors such as 11 which form a matrix array for controlling individual liquid crystal pixels such as 12. The gates of the transistors 11 of each row are connected together and to a scan driver 13 whereas the drains of the transistors 11 of each column are connected together and to respective output buffers 5. Digital data and control signals are supplied to a column data driver 14 including DACs of the type shown in FIG. 1 or FIG. 2 of the accompanying drawings.
The data lines are also connected to a precharging circuit 15 which receives a precharge control signal. The purpose of this arrangement is to reduce the slew-rate requirement on the output buffers 5.
In order to maintain DC balance of the liquid crystal, it is usual to drive the pixels with alternating polarity voltages. For example, the polarity may be reversed after each line or frame of data has been supplied to the display. Thus, the maximum slew-rate capability of the output buffers 5 limits the refresh rate of the display because the required pixel voltage during a refresh cycle has to be achieved from the opposite polarity pixel voltage during the previous refresh cycle.
In the arrangement shown in FIG. 3, before the start of each refresh cycle, the precharge circuit 15 precharges all of the data lines to a fixed voltage so as to reduce the voltage change which must be achieved across each pixel. This reduces the maximum slew-rate required of the output buffers 5.
Techniques of this type are disclosed in EP 0 899 714, EP 0 899 713 and EP 0 899 712. In this case, the precharge circuit 15 precharges the datalines to approximately half of the maximum pixel voltage. Thus, in the worst case where a maximum pixel voltage is to be established on a pixel which was previously charged to the maximum pixel voltage of the opposite polarity, the maximum slew-rate is decreased by a factor of four.
According to a first aspect of the invention, there is provided a digital-to-analog converter comprising: a first converter stage for performing first digital-to-analog conversion of the m most significant bits of a k bit input signal; a precharging circuit for precharging an output load to a precharge voltage in accordance with the result of the first conversion: and a second converter stage for performing a second digital-to-analog conversion of the n least significant bits of the k bit input signal.
The sum of m and n may be equal to k.
The first stage may be arranged to select first and second voltages of a plurality of reference voltages in accordance with the m most significant bits.
The plurality of reference voltages may comprise 2m+1 reference voltages.
The first and second voltages may have consecutive values.
The magnitude of the first voltage may be greater than the magnitude of the second voltage and the magnitude of the precharge voltage may be less than or substantially equal to the magnitude of the first voltage and greater than or substantially equal to the magnitude of the second voltage.
The magnitude of the precharge voltage may be substantially equal to the arithmetic mean of the magnitudes of the first and second voltages.
The precharge voltage may be substantially equal to one of the first and second voltages. The precharge voltage may be substantially equal to the second voltage. The first stage may have first and second outputs for the first and second voltages, respectively, and the precharging circuit may comprise a first switch for connecting an output of the converter to one of the first and second outputs during a precharge phase.
The precharging circuit may comprise a second switch for disconnecting an output of the second stage from the output of the converter during the precharge phase.
An output buffer may be connected between the output of the second stage and the second switch. The output buffer may have differential inputs, a first of which is connected to the output of the second stage and a second of which is connected to one of the first and second outputs.
The first stage may comprise an m-to-2m decoder and first and second 2m-to-1 multiplexers.
The second stage may be arranged to convert the n least significant bits to a voltage between the first and second voltages.
The second stage may be arranged to perform a linear conversion.
The second stage may comprise a potential divider, an n-to-2n decoder and a 2n-to-1 multiplexer.
The second stage may comprise a plurality of capacitors and a plurality of switches for selectively connecting the capacitors to receive the first or second voltage in accordance with the n least significant bits.
According to a second aspect of the invention, there is provided an active matrix liquid crystal display comprising a converter according to the first aspect of the invention.
It is thus possible to provide a DAC having a substantially increased conversion speed. By performing precharging of an output load on the basis of an initial or first conversion process, the second conversion stage is required to provide, at worst, a much smaller voltage change so that the total conversion period may be reduced for a given drive capability. In cases where an output buffer is provided, the maximum slew-rate requirement of the buffer can be substantially reduced. Alternatively, for a given speed requirement, the design of the converter and, when present, the buffer can be substantially simplified. Also, a reduced power consumption can be achieved.